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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.cirrus.com cs4922 mpeg/g.729a audio decoder system features l dsp optimized for audio decode, 24-bit fixed point w/48-bit accumulator l on-chip functional blocks include: - dsp with ram and rom memories - cd quality stereo dac with output filtering - mono output & digital volume control - s/pdif transmitter, bidirectional pcm audio port - internal phase locked loop for clocking - dedicated compressed serial input interface l mpeg-1 & mpeg-2 layers 1 & 2 with all sample/bit rates and ancillary data support. l mpeg-1 & mpeg-2 packetized audio stream and elementary stream input l g.729a audio decode l pcm synthesis for auxiliary audio l pin compatibility with cs4920a and primary feature/firmware compatible l +5 volt only cmos, 44 pin plcc description the cs4922 is a complete audio decompression sub- system implemented in a single high integration mixed signal cmos chip. the cs4922 has been widely used in direct broadcast system set-top boxes and proprietary embedded systems which pull compressed audio from local system memory. the cs4922 is tailored to include the necessary hard- ware and firmware to ensure proper audio/video synchronization for mpeg-2 audio decompression. in addition to audio decoding this programmable dsp solu- tion provides robust error concealment and feature implementations like ancillary data support and pcm synthesis. the cs4922 can also support the decode of other com- pression standards such as g.729a with a separate download image. the flexible architecture of the cs4922 provides the ability to mix compressed audio with data from the auxiliary pcm port. ordering information CS4922-CL 44-pin plcc cdb4922 evaluation board vd1 vd4 sck/scl sda/cdout cdin cs req va+ serial control port (spi or i 2 c) auxlr auxin auxout auxclk fsync sclk sdata auxiliary serial audio port serial audio port reset 90_clk boot 33 bit counter dgnd1 dgnd4 dsp flt clkin extck altclk clkout pll + clock manager stereo dac aoutm aoutl aoutr aes/ebu - s/pdif tx transmitter programmable io/ pins pio xf1 xf2 xf3 xf4 agnd1 agnd2 jul 99 ds227pp2
cs4922 2 table of contents 1 characteristics and specifications .......................................................4 analog characteristics .........................................................................4 d/a interpolation filter characteristics.......................................4 absolute maximum ratings ....................................................................5 recommended operating conditions ................................................5 digital characteristics ..........................................................................5 switching characteristics - clocks .................................................6 switching characteristics - external flags ................................6 switching characteristics - programmable input/output ....... 6 switching characteristics - boot initialization...........................7 switching characteristics - control port (spi mode)...............8 switching characteristics - control port (i 2 c mode) .............10 switching characteristics - serial audio port ..........................12 switching characteristics - auxiliary digital audio port .....13 2 typical connection diagram.....................................................................14 3 theory of operation ...................................................................................15 3.1 introduction .....................................................................................................15 4 peripherals .....................................................................................................15 4.1 clock manager ................................................................................................15 4.2 33-bit counter .................................................................................................16 4.3 digital to analog converter .............................................................................16 4.4 digital audio transmitter .................................................................................17 4.5 audio serial input port ....................................................................................17 4.6 auxiliary digital audio port ..............................................................................17 4.7 serial control port ...........................................................................................17 4.7.1 i 2 c mode ...............................................................................................18 4.7.2 rise time on scl/sck ........................................................................20 4.7.3 spi mode ..............................................................................................20 4.8 external flag pins ...........................................................................................22 5 boot procedure ............................................................................................23 6 power supply and grounding .................................................................24 7 dac filter response plots .......................................................................26 8 pin descriptions..............................................................................................27 power supplies ...............................................................................................27 digital-to-analog converter .............................................................................28 serial audio port .............................................................................................28 digital audio transmitter .................................................................................28 clock manager ................................................................................................28 control ............................................................................................................29 serial control port ...........................................................................................30 auxiliary digital audio port ..............................................................................30 9 parameter definitions .................................................................................31 10package dimensions ...................................................................................32 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ i 2 c is a registered trademark of philips semic onductor. preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. cirrus logic, inc. has made best effort s to ensure that the information contained in this document is accurate and reliable. however, the information is subject to change without notice and is provi d ed as is without warranty of any kind (express or implied). no responsibility is assumed by cirrus logic, inc. for the use of this information, nor for inf ringements of patents or other rights of third parties. this document is the property of cirrus logic, inc. and implies no license under patents, copyrights, tradem arks, or trade secrets. no part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electron ic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc. items from any cirrus logic website or disk may be printed for use by the user. however, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form o r by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of cirrus logic, inc.furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of cirrus logic, inc. the names of products of cirrus logic, inc. or ot her vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. a list of cirrus logic, inc. trade- marks and service marks can be found at http://www.cirrus.com.
cs4922 3 list of figures figure 1. boot timing ......................................................................................... 7 figure 2. spi control port timing ....................................................................... 9 figure 3. i 2 c ? control port timing ................................................................... 11 figure 4. serial audio port timing .................................................................... 12 figure 5. auxiliary audio port timing ............................................................... 13 figure 6. typical connection diagram ............................................................. 14 figure 7. clkout generation circuit .............................................................. 16 figure 8. dac ................................................................................................... 16 figure 9. auxiliary data input formats ............................................................. 17 figure 10. auxiliary data output formats .......................................................... 17 figure 11. multi-channel auxiliary data formats ................................................ 18 figure 12. control port timing, i 2 c ? write ......................................................... 19 figure 13. serial control port ............................................................................. 19 figure 14. control port timing, i 2 c ? read ......................................................... 20 figure 15. i 2 c ? connection diagram ................................................................. 21 figure 16. control port timing, spi write .......................................................... 21 figure 17. control port timing, spi read .......................................................... 22 figure 18. cs4922 suggested layout ............................................................... 24 figure 19. cs4922 surface mount decoupling layout ...................................... 25 figure 20. dac frequency response ................................................................ 26 figure 21. dac phase response ...................................................................... 26 figure 22. dac transition band ......................................................................... 26 figure 23. dac passband ripple ....................................................................... 26
cs4922 4 1 characteristics and specifications analog characteristics (t a = 25 c; va+, vd+ = 5v; clkin = 27 mhz; full-scale output sinewave, 1.125 khz; word clock = 48 khz (pll in use); logic 0 = gnd, logic 1 = vd+; measurement bandwidth is 20 hz to 20 khz; local components as shown in "typical connection diagram"; spi mode, i 2 s audio data; unless otherwise specified.) notes: 1. 10 k w , 100pf load for each analog signal (left, right). 30 k w , 100pf load for analog mono signal. d/a interpolation filter characteristics (see figures 20 through 23) * refer to parameter definitions on page 31 of this data sheet. specifications are subject to change without notice. parameter* symbol min typ max units dynamic performance dac resolution 16 - - bits dac differential nonlinearity dnl - - 0.9 lsb total harmonic distortion aoutl, aoutr (note 1) aoutm thd - 0.01 0.02 0.015 0.03 % instantaneous dynamic range aoutl, aoutr (note 1) (dac not muted, a weighted) aoutm idr 85 80 90 85 -db interchannel isolation (note 1) - 85 - db interchannel gain mismatch - - 0.2 db frequency response -3.0 - +0.2 db full scale output voltage aoutl, aoutr (note 1) aoutm 2.66 2.7 2.88 3.0 3.2 3.3 vpp gain drift - 100 - ppm/c deviation from linear phase - - 5 deg out of band energy (fs/2 to 2fs) - -60 - db analog output load resistance: capacitance: 8 - - - - 100 k w pf power supply power supply rejection (1 khz) - 40 - db power supply consumption va+ vd+ - - 20 100 40 140 ma ma parameter symbol min typ max units passband (to -3 db corner) (fs is conversion freq.). 0 - 0.476fs hz passband ripple. - - 0.1 db transition band. 0.442fs - 0.567fs hz stop band. 3 0.567fs - - hz stop band rejection. 50 - - db stop band rejection with ext. 2fs rc filter. 57 - - db group delay. - 12/fs - s
cs4922 5 absolute maximum ratings (agnd, dgnd = 0v, all voltages with respect to ground.) warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd = 0v; all voltages with respect to ground.) digital characteristics (t a = 25 c; va+, vd+ = 5v 10%; measurements performed under static conditions.) notes: 2. not valid for pin numbers 9, 12, 13, and 30 which are configured with on-chip pull-down resistors. not valid for pin number 29 which is a static input signal and should be tied to either vd+ or dgnd. parameter symbol min max units dc power supplies: positive digital positive analog | | va+ | - | vd+ | | vd+ va+ -0.3 -0.3 - 6.0 6.0 0.4 v v v input current, any pin except supplies i in - 10 ma digital input voltage v ind -0.3 (vd+) + 0.4 v ambient operating temperature (power applied) t amax -55 125 c storage temperature t stg -65 150 c parameter symbol min typ max units dc power supplies: positive digital positive analog | | va+ | - | vd+ | | vd+ va+ 4.50 4.50 - 5.0 5.0 - 5.50 5.50 0.4 v v v ambient operating temperature t a 0-70c parameter symbol min typ max units high-level input voltage v ih tbd 2.25 - v low-level input voltage v il --0.8v high-level output voltage at i o = -2.0 ma v oh vd x 0.9 - - v low-level output voltage at i o = 2.0 ma v ol --vd x 0.1v input leakage current (note 2) i in --1.0 m a
cs4922 6 switching characteristics - clocks (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 20pf) switching characteristics - external flags (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 20pf) notes: 3. assumes 2k w pull-up to 5v supply on xf1-xf4 pins. switching characteristics - programmable input/output (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 20pf) parameter symbol min typ max units master clock frequency clkin 27 mhz master clock duty cycle cyck 40 50 60 % clock output clkout - - 256 fs mhz parameter symbol min typ max units rise time of xf1-xf4 (note 3) t rxf 200 ns fall time of xf1-xf4 t fxf 100 ns parameter symbol min typ max units i_o = 0 input frequency f pio 350 khz risetime of pio t rpio 200 ns fall time of pio t fpio 200 ns i_o = 1 rise time of pio t rpo 200 ns fall time of pio t fpo 200 ns
cs4922 7 switching characteristics - boot initialization (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 20pf) notes: 4. the mode of the serial control port is selected by cs . cs = 1 is i 2 c a . cs = 0 is spi mode. 5. this delay is necessary after any rising edge of reset to allow time for the part to initialize and for the on-board pll to stabilize. parameter symbol min max units boot setup time to reset rising t bsu 350 - ns reset rising to boot hold time t bh 450 - ns cs setup time to reset rising (note 4) t cssu 200 - ns reset rising to cs hold time t csh 400 - ns reset low time t rlow 50 - m s sck/scl delay time from reset rising (note 5) t rsc 2-ms sck/scl falling to cs rising on last byte of download t sfcr 3- m s boot reset sck/scl t bsu t bh t rlow t cssu t csh t rsc cs (spi) cs (i c) 2 t sfcr figure 1. boot timing
cs4922 8 switching characteristics - control port (spi mode) (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 20pf) notes: 6. data must be held for sufficient time to bridge 300(50) ns transition time of sck/scl. 7. cdout should not be sampled during this time period. 8. req will only go high if there is no data in scpout at the rising edge of scl/sck during a read operation as shown. dsp frequency is 20 mhz. pull-up resistor is 2 k w . c l = 20 pf. 9. if req went high as indicated in note 7, then req will hold high at least until the next rising edge of sck/scl. if data is in scpout at this time req will go active low again. this condition should be treated as a new read process. address and r/w bit should be sent again. parameter symbol min max units spi mode (cs = 0) sck/scl clock frequency (slow mode) (fast mode) f sck f sck - - 350 2000 khz cs falling to sck/scl rising (slow mode) t css 20 - ns rise time of both cdin and sck/scl lines (slow mode) t r -50ns fall time of both cdin and sck/scl lines (slow mode) (fast mode) t f t f - - 300 50 ns ns sck/scl low time (slow mode) (fast mode) t scl t scl 1100 150 - - ns ns sck/scl high time (slow mode) (fast mode) t sch t sch 1100 150 - - ns ns setup time cdin to sck/scl rising (slow mode) (fast mode) t cdisu 250 50 - - ns ns hold time sck/scl rising to cdin (note 6) t cdih 50 - ns transition time from sck/scl to cdout valid (note 7) t scdov -40ns time from sck/scl rising to req rising (note 7) t scrh -200ns rise time for req (note 8) t rr -50ns fall time for req (note 9) t rf -20ns hold time for req from sck/scl rising (note 9) t scrl 0-ns time from sck/scl falling to cs rising t sccsh 20 - ns high time between active cs t csht 200 - ns
cs4922 9 t css t scl t r t sch t cdisu t scdov t cdih t scdov t rf t r msb msb a0 r/w a6 a5 cs sck/scl cdin cdout req t sccsh t scrl t rh t scrh t csht cs sck/scl cdin req cdout lsb lsb 6 7 5 a6 t cscdo tri-state figure 2. spi control port timing
cs4922 10 switching characteristics - control port (i 2 c mode) (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = dgnd, logic 1 = vd+, c l = 20pf) notes: 10. use of i 2 c a bus compatible interface requires a license from philips. 11. data must be held for sufficient time to bridge the 300ns transition time of sck/scl. 12. this rise time is shorter than the i 2 c specifications recommend, please refer to the section on scp communications for more information. 13. req will only go high if there is no data in the scpout register at the rising edge of scl/sck during a read operation as shown. dsp frequency is 20 mhz. pull-up resistor is 2 k w c l = 20pf. 14. if req went high as indicated in note 13 then req will hold high at least until the next rising edge of sck/scl. if data is in the scpout register at this time req will go active low again. this condition should be treated as a new read process. the address and r/w should be sent again following a new start condition. parameter symbol min max units i 2 c a mode (cs =1) (note 10) sck/scl clock frequency (slow mode) (fast mode) f scl 100 400 khz bus free time between transmissions t buf 4.7 m s start condition hold time (prior to first clock pulse) t hdst 4.0 m s clock low time slow fast t low 4.7 1.2 m s clock high time slow fast t high 4.0 1.0 m s sda setup time to sck/scl rising t sud 250 ns sda hold time from sck/scl falling (note 11) t hdd 0 m s rise time of both sda and sck/scl (note 12) t r 50 ns fall time of both sda and sck/scl t f 300 ns time from sck/scl falling to cs4920 ack t sca 40 ns time from sck/scl falling to sda valid during read operation t scsdv 40 ns time from sck/scl rising to req rising (note 13) t scrh 200 ns hold time for req from sck/scl rising (note 14) t scrl 0ns rise time for req (note 13) t rr 50 ns fall time for req (note 14) t rf 20 ns setup time for stop condition t susp 4.7 m s
cs4922 11 t low t sud t buf t scsdv t hdd t r t high t f t sca t hdst msb a0 a6 a5 cs sck/scl sda req r/w ack stop start 01 6 78 0 t cssta t rf t susp t scrl t rr cs sck/scl req sda ack 7 8 lsb stop t scrh t cssto figure 3. i 2 c ? control port timing
cs4922 12 switching characteristics - serial audio port (t a = 25 c; va+, vd+ = 5v; inputs: logic 0 = gnd, logic 1 = vd+; c l = 20 pf) notes: 15. the table above assumes data is output on the falling edge and latched on the rising edge. the sclk edge is selectable in setting the edg bit in the asicn register. the diagram is for edg = 1. parameter symbol min typ max units sclk frequency - - 12.5 mhz sclk pulse width low t sckl 25 - - ns sclk pulse width high t sckh 25 - - ns sclk rising to fsync edge delay (note 15) t sfds 20 - - ns sclk rising to fsync edge setup (note 15) t sfs 20 - - ns sdata valid to sclk rising setup (note 15) t sss 20 - - ns sclk rising to sdata hold time (note 15) t ssh 20 - - ns rise time of sclk t sclr --20ns sckh t sfs t sfds t sss t ssh t sckl t sdata sclk fsync sclr t figure 4. serial audio port timing
cs4922 13 switching characteristics - auxiliary digital audio port notes: 16. fs determined by clock input rate and configuration of on-chip pll. 17. auxclk frequency selectable @ 32, 64, or 128 fs via auxcn register bits 1:0. parameter symbol min typ max units input sample rate (note 16) fs 16 - 48 khz auxclk period (note 17) tsclk - 1/(32fs) 1/(64fs) 1/(128fs) -ns auxclk to auxlr valid tlrun 0 - 25 ns auxclk to auxout data valid tdoun 0 - 25 auxin data setup time to auxclk tdisu 50 - - ns auxin data hold time from auxclk tdiho 3 - - ns auxclk auxlr auxout auxin fs t sclk t lrun t doun t disu t diho figure 5. auxiliary audio port timing
cs4922 14 2 typical connection diagram cs4922 ferrite bead + 1 m f 0.1 m f vd1 vd4 va+ fsync sclk sdata sck/scl sda/cdout cdin cs req reset boot pio clkin aoutl aoutr tx flt 27 mhz + 1 m f0.1 m f + 40k 0.0022 m f npo > 1.0 m f 600 extck dgnd1 dgnd4 agnd2 0.47 m f right audio left audio +5v supply altclk + 1 m f0.1 m f xf1 +5v 2.0k 90_clk +5v note: 1 capacitor pair per power supply ferrite bead 7 17 25 43 23 22 21 20 3 2 4 1 44 41 40 24 27 28 6182642 33 29 19 31 5 36 39 38 34 + 40k 0.0022 m f npo > 1.0 m f 600 agnd1 aoutm mono audio 37 + 40k 0.0022 m f npo > 1.0 m f 600 30 clkout micro controller audio source s/pdif receiver auxin 9 serial codec auxout 8 auxclk 11 auxlr 10 xf2 16 xf3 15 xf4 14 program rom 10k 2.0k 2.0k 2.0k 2.0k figure 6. typical connection diagram
cs4922 15 3 theory of operation 3.1 introduction the cs4922 is a complete audio subsystem on a chip. it consists of a general-purpose digital signal processor (dsp), and a number of supplementary analog and digital blocks. these supplementary blocks include a pll clock multiplier, a serial au- dio input port, an auxiliary serial audio port, a cd quality stereo digital-to-analog converter (dac), an aes/ebu - s/pdif compatible digital audio transmitter, and a serial control port. figure 6 shows a typical connection diagram for the cs4922 in which a micro controller is used for loading the program code. the cs4922 is ram based audio decoder that can be used to process compressed digital audio sig- nals. serial audio data broadcast on networks such as cable tv, direct broadcast satellite tv, or the telephone system can be decompressed and con- verted to standard analog and digital signals. a wide variety of standard and proprietary decom- pression algorithms can be supported. cs4922 application code is available which per- forms industry standard mpeg 1 and 2, layers i and ii. application code is also available for g.729a decode. the dsp has a 24-bit fixed point data path, 5k words of program ram, and 3k words of data ram. the execution unit includes a 48-bit accu- mulator. the dsp can provide up to 12 mips. either compressed digital audio data or pcm data can be delivered. for analog reproduction of the digital input, a ste- reo dac using delta-sigma architecture is built-in. switched-capacitor filters perform most of the re- construction process. only a simple external pas- sive filter is needed to complete reconstruction. in addition to the analog output, an aes/ebu - s/pdif compatible output is provided. this allows the designer the flexibility of transmitting the audio data in a standard digital format to an external sys- tem. to facilitate the downloading of dsp code to the cs4922, a serial control port, communicating in ei- ther i 2 c a or spi format, is used. this port may also be used during run time to issue control commands to the dsp. 4 peripherals six on-chip peripherals make the audio decoder ideal for decoding broadcast digital audio signals. it has a pll clock manager, a cd quality dac, a digital audio transmitter, a three pin serial port for audio data input, a serial bi-directional auxiliary port for digital audio data, and an spi/i 2 c port for serial control information. each peripheral has i/o mapped data, control, and status registers. many peripherals can also generate interrupts. 4.1 clock manager the clock manager is primarily a clock multiplier circuit that takes a reference frequency of 27 mhz on clkin which is used for deriving internal clocking. at the heart of the clock manager circuit is a pll (phase-locked loop) circuit. the pll is configured by software to produce the appropriate dsp clock for the desired sample rate. all other in- ternal clocks required for the dac and other pe- ripherals are derived from this root clock. the plls internal vco requires a capacitor to be connected to the flt pin (pin 31). the typical val- ue of the flt capacitor is 0.47 f, which is suffi- cient for all allowable clkin input frequencies. it must be stressed that the best analog performance can only be achieved by placing the capacitor as close as possible to the flt pin and that the proper layout precautions be taken to avoid noise coupling onto the flt pin. the clkout pin is a divided version of the dsp clock. a diagram of the clkout generation cir- cuit is shown in figure 7.
cs4922 16 the dsp clock is divided by a programmable di- vider and an additional divide by 2 before being output. the divider output is determined by the val- ue of the q value which can be accessed through the application software. the divide by 2 guaran- tees a 50% duty cycle output. the q value provides effective divides ranging from 1 to 1024, which means the frequency of clkout can vary from the dsp clock frequency divided by 2 to the dsp clock frequency divided by 2048. clkout can be used to synchronize external devices or generate most compressed bit rate clocks. 4.2 33-bit counter the 33-bit-counter can be used to support mpeg synchronization of audio and video. this loadable counter is targeted to operate at 90 khz. the 90 khz clock may be derived from a 27 mhz mas- ter clock provided at clkin (if available) or from a 90 khz clock provided at pin 19 90_clk. the se- lection of the counter clock is made via the register bit div which is accessible through the application code. when set, the div bit divides the clock at clkin by 300 and provides the divided clock to 33-bit-counter. 4.3 digital to analog converter the digital to analog converter (dac) is a dual channel cd quality dac. it is designed with delta sigma architecture. the baseband audio is interpo- lated to 128fs (192fs) before going into the modu- lator. the modulator is third order and is followed by a 1 bit dac/switch capacitor filter stage. an ex- ternal passive filter completes the reconstruction process. the output is single ended with a drive ca- pability down to 8 k w . figure 8 is a block diagram of the dac. the interpolation filter produces images which are attenuated by at least 56 db from .584fs to 128fs (192fs). at a 48 khz sample rate, a full scale signal at 20 khz will produce an image at 28 khz which is attenuated by more than 60 db. the out-of-band quantization noise from the delta sigma modulator extends from .417fs to 128fs (192fs). this noise is attenuated by the switch ca- pacitor filter and the continuous time filters. the total quantization noise and thermal noise from the analog filters integrated over the .417fs to 128fs (192fs) is more than 50 db below full scale power. 2 q dsp clock clkou t figure 7. clkout generation circuit aoutl aoutr i/o data bus interpolation filter modulator switched capacitor filter interpolation filter modulator switched capacitor filter 16 d a c reg d a c l d a c r sreg sreg figure 8. dac
cs4922 17 4.4 digital audio transmitter the transmitter encodes digital audio data accord- ing to the sony ? /philips ? digital interface format (s/pdif) or the aes/ebu interface format. the encoded data is output on the tx pin. more infor- mation on the s/pdif and aes/ebu standards are available from crystals application note library. 4.5 audio serial input port the audio serial input port has a three pin interface consisting of fsync, sclk, and sdata. fsync is only used to frame data when the audio data is in a pcm format. systems, such as mpeg decoders, which use the audio serial input port for compressed audio data should tie fsync to +5v. sclk used to clock sdata (serial data input) into an internal fifo. the active edge of sclk is de- termined by the application code running on the cs4922. consult the documentation for each ap- plication download to determine your system re- quirements. 4.6 auxiliary digital audio port the cs4922 auxiliary port provides a path for the internal dsp core to directly read and write framed pcm digital audio data. the auxiliary port is de- signed to operate in a full duplex mode that can support simultaneous pcm input and output. it is important to note that the cs4922 always masters the audio clocks on the auxiliary digital audio port. the port has the capability to support two digital audio formats. the formats are illustrated in fig- ures 9, 10, and 11. the input and output formats are always configured to operate in the same mode. the input and output sampling rates are the same as the sample rate for the on-chip dac. the aux port can support 18 bit samples at 64fs (i 2 s for- mat) or 20 bit samples at 128fs (left justified for- mat). the cs4922 auxiliary digital audio port physically is implemented with four device pins: auxclk pin 11, auxlr pin 10, auxin pin 9, and aux- out pin 8. auxclk is utilized as the primary synchronous clock. auxout is the serial audio data output pin and auxin is the serial audio data input pin. auxlr is an output pin used for fram- ing the auxiliary digital audio port. auxlr cycles at the same fs as the on-chip stereo dac. fs is programmed by the dsp. auxlr and auxout transition with the falling edge of auxclk. the rising edge of auxclk samples auxin. 4.7 serial control port the serial control port (scp) can operate in i 2 c or spi compatible modes. in either mode, the control port performs eight bit transfers and is always con- figured as a slave. as a slave, it cannot drive the clock signal nor initiate data transfers. the port can request to be serviced by activating the req pin. the port is an asynchronous interface which pro- vides interrupts and handshaking signals to allow msb lsb left right msb lsb i s input 2 auxclk auxin auxlr figure 9. auxiliary data input formats msb lsb left right msb lsb auxlr auxclk auxout i s output 2 figure 10. auxiliary data output formats
cs4922 18 communication between the on-chip dsp and an off-chip device such as a micro controller. figure 13 shows a block diagram of the port. 4.7.1 i 2 c mode the status of cs sets the mode of the scp during a hardware and software reset. if cs is high during a reset the mode is i 2 c. note that in most systems where i 2 c is the preferred control mode, cs is con- nected to the digital supply. for normal i 2 c operation scl/sck, sda, and req are used. cs and cdin are typically connect- ed to the digital supply. scl/sck is the serial clock input which is always driven by an external device. sda is the serial data input/output signal. req is the active low request signal, which is driv- en low when there is valid data in the serial control port output scpout register. as an i 2 c compatible port, data is communicated on the sda pin and is clocked by the rising edge of scl/sck. the philips i 2 c bus specification pro- vides details of this interface. note the cs4922 does not meet the rise time specification of the scl/sck signal. for more details please refer to the section on rise time of scl/sck. figure 12 shows the relative timing necessary for an i 2 c write operation for a single byte. a write is defined as the transfer of data from an i 2 c bus master to the cs4922 serial control port. a transfer is initiated with a start condition followed by a 7 bit address and a read/write bit (set low for a write). this address is the address assigned to the device being written to during the transfer. in the case of the cs4922, this address is stored in the scpcn register. immediately following power up, the cs4922's address checking enable (aen) bit is set to zero. the aen bit must be set high for the cs4922 to compare the address of the intended i 2 c device on the bus to its internal address. this means the cs4922 will respond to any address on the i 2 c bus until its address is initialized and address checking is enabled. to avoid bus conflicts the cs4922 should be held in reset (reset active low) until the master is ready to communicate with the cs4922 and sets the address in the scpcn. the address can only be set using the i 2 c bus interface, so the master should use the intended i 2 c address when downloading microcode to the cs4922 to avoid conflict with other devices on the bus. once the microcode is loaded into the cs4922 the micro- code should either initialize the i 2 c address or pro- vide a means for the master to program the i 2 c address. if the cs4922 is the only device on the i 2 c bus, address checking is optional. however, i 2 c bus protocol is still required. in other words, the ad- dress bits and read/write bit are still required. if a write to the cs4922 is specified, 8 bits of data on sda will be shifted into the input shift register as shown in figure 13. when the shift register is full, the 8 bit data is transferred to the serial control port input (scpin) register on the falling edge of the 8th data bit and an acknowledge (ack) is sent back to the master.. auxlr auxclk auxout lsb msb 20 clks 64 clks 64 clks lsb msb lsb msb lsb msb lsb msb lsb msb msb auxout #1 auxout #3 auxout #5 auxout #2 auxout #4 auxout #6 20 clks 20 clks 20 clks 20 clks 20 clks 20 clks auxin #1 auxin #3 auxin #2 auxin #4 20 clks 20 clks 20 clks auxin figure 11. multi-channel auxiliary data formats
cs4922 19 if the cs4922 fails to ack it is possible that the byte was rejected and it should be transmitted again. if the second attempt fails the cs4922 should be issued a hardware reset to reinitialize the communication path. if the dsp core of the cs4922 wants to send a byte to the master, it first writes the byte to the serial control port output (scpout) register. a write to the scpout sets the request pin (req ) active low . the master must recognize the request and issue a read operation to the dsp. figure 14 shows the rel- ative timing of a single byte read. the master must send the 7 bit address (if address checking is en- abled it must match the address in the scpcn reg- ister) and the read bit. for i 2 c protocol, it is always the device receiving the transfer that must ack. therefore, the cs4922 will ack the address and the read bit. after the ack by the cs4922 (the fall- ing edge of scl/sck), the serial shift register is loaded with the byte to be sent and the most signif- icant bit is placed on the sda line. the 8 bit value in the serial shift register is shifted out by the master. the data is valid on the rising edge of scl/sck and transitions immediately fol- ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack d7 d6 d5 d4 d3 d2 d1 d0 ack sda scl/sck sda scl/sck start stop figure 12. control port timing, i 2 c ? write 24 state machine output control interrupt control scpout scpin int i/o data bus 24 8 8 sreg 8 8 scpcn cs req sck/scl cdin sda/ cdout m0 figure 13. serial control port
cs4922 20 lowing the falling edge. for i 2 c the req line will be de-asserted immediately following the rising edge of the last data bit of the current byte being transferred, if there is no data in the scpout reg- ister. the req line is guaranteed to stay de-assert- ed (high) until the rising edge of the scl/sck for the ack. this signals the host that the transfer is complete. if there is data placed in scpout prior to the ris- ing edge of scl/sck for the last data bit, then req will remain asserted (low). immediately fol- lowing the falling edge of scl/sck for the ack, the new data byte will be loaded into the serial shift register. the host should continue to read this new byte. it is important to note that once the data is in the shift register, clocks on the scl/sck line will shift the data bits out of the shift register. a stop condition on the bus will not prevent this from oc- curring. the host must read the byte prior to any other bus activity or the data will be lost. if data is placed in scpout after the rising edge of scl/sck for the last data bit, but before the rising edge of scl/sck for the ack, req will not be asserted until after the rising edge of scl/sck for the ack. this should be treated as a completed transfer. the data written to scpout will not be loaded into the shift register on the falling edge of scl/sck for the ack. therefore, a new read op- eration is required to read this byte. 4.7.2 rise time on scl/sck the philips i 2 c bus specification allows for rise times of the scl/sck line up to 1 m s. the cs4922 does not meet this specification. if the i 2 c bus mas- ter(s) has a rise time in excess of 50 ns the cs4922 will be unable to reliably communicate across the bus. in some systems a stronger pull-up resistor on the scl/sck line will provide the rise time needed for proper operation, but this is only helpful when the current rise time is near 50 ns. in cases where the cs4922 will be used in a system where a longer rise time on scl/sck is expected, a cmos com- patible buffer should be used. figure 15 shows the necessary connections. note the buffer is only used for the scl/sck connecting directly to the cs4922. other devices on the i 2 c bus may need to hold scl/sck low while accepting data. 4.7.3 spi mode the status of cs sets the mode of the scp during a hardware and software reset. if cs is low during a reset the mode is spi. it is important to note that cs should be low when either a hardware of software reset is issued to ensure the mode remains spi. ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w ack d7 d6 d5 d4 d3 d2 d1 d0 sda scl/sck sda scl/sck start stop req req figure 14. control port timing, i 2 c ? read
cs4922 21 for normal spi operation scl/sck, cs , cdin, cdout and req are used. scl/sck is the serial clock input which is always driven by an external device. cs is the active low enable signal. cdin is the control data input. cdout is the control data output. req is the active low request signal, which is driven low when there is valid data in the serial control port output scpout register. as an spi compatible port, data is communicated on the cdin and cdout pins and is clocked by the rising edge of scl/sck. cs is used to select the device on which the cdin and cdout sig- nals will be valid. figure 16 shows the relative timing necessary for an spi write operation of a single byte. a write is defined as the transfer of data from an spi bus mas- ter to the cs4922 serial control port via cdin. a transfer is initiated with cs being driven active low. this is followed by a 7 bit address and a read/write bit (set low for a write). for spi mode, this address is typically not used, however it is still necessary to clock an address across the bus fol- lowed by the read/write bit. if a write to the cs4922 is specified, 8 bits of data on cdin will be shifted into the input shift register as shown in figure 13. when the shift register is full, the 8 bit data is transferred to the serial con- trol port input (scpin) register on the falling edge of the 8th data bit. if the dsp core of the cs4922 wants to send a byte to the master, it first writes the byte to the serial control port output (scpout) register. a write to the scpout sets the request pin (req ) active low. the master must recognize the request and is- sue a read operation to the dsp. figure 17 shows the relative timing of a single byte read. the master must send the 7 bit address (if address checking is enabled it must match the address in the scpcn register) and the read bit. after the falling edge of scl/sck for the read/write bit, the serial shift reg- ister is loaded with the byte to be sent and the most significant bit is placed on the cdout line. i c 2 controller scl sda vcc 2k w 2k w vcc cs4922 scl/sck sda to other i c devices 2 figure 15. i 2 c ? connection diagram cs scl/sck cs scl/sck cdin cdin ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w d7 d6 d5 d4 d3 d2 d1 d0 figure 16. control port timing, spi write
cs4922 22 the 8 bit value in the serial shift register is shifted out by the master. the data is valid on the rising edge of scl/sck and transitions immediately fol- lowing the falling edge. for spi, the req line will be de-asserted immediately following the rising edge of the second to last data bit, of the current byte being transferred, if there is no data in the scpout register. the req line is guaranteed to stay de-asserted (high) until the rising edge of the scl/sck for the last data bit. this signals the host that the transfer is complete. if there is data placed in scpout prior to the ris- ing edge of scl/sck for the second to last data bit, then req will remain asserted (low). immediately following the falling edge of scl/sck for the last data bit, the new data byte will be loaded into the serial shift register. the host should continue to read this new byte. it is important to note that once the data is in the shift register, clocks on the scl/sck line will shift the data bits out of the shift register. the host should read the byte prior to any other bus activity or the data will be lost. if cs is de-asserted sck/scl will not shift the data out. however the data is still in the shift register. once cs becomes active (low) each scl/sck will shift the data out of the register. if data is placed in scpout after the rising edge of scl/sck for the second to last data bit, but before the rising edge of scl/sck for the last data bit, req will not be asserted until after the rising edge of scl/sck for the last data bit. this should be treated as a completed transfer. the data written to scpout will not be loaded into the shift register on the falling edge of scl/sck for the last data bit. therefore, a new read operation is required to read this byte. 4.8 external flag pins the cs4922 has four external flag pins: xf1-xf4. an external pull-up (2.2 k w typical) is required for proper operation on each pin. the usage of the xf pins is completely defined by the application code running on the cs4922. the mpeg application, for example, uses xf1 as a compressed data throttle indicator. when the xf1 pin is low, the host may continue to send com- pressed data to the cs4922. when xf1 is high, the cs scl/sck cs scl/sck cdin cdin ad6 ad5 ad4 ad3 ad2 ad1 ad0 r/w cdout d7 req cdout d6 d5 d4 d3 d2 d1 d0 req figure 17. control port timing, spi read
cs4922 23 host should hold off data delivery until xf1 falls low once again. please see the documentation for the application code being used in your system for a complete de- scription. 5 boot procedure the cs4922 is a ram based audio decoder. con- sequently, program and data ram must be loaded from external memory after power up or any other time a new program needs to be downloaded. dur- ing the loading procedure (boot), data is transferred through the serial control port to program and data memory. this procedure is controlled by a pro- gram stored internally in rom. the boot procedure is initiated by a low to high transition of the reset (reset ) pin with the boot pin high. this initializes the program counter to lo- cation 1000 h , the first location in rom which pre- pares the cs4922 for download. after the rom program transfers data from the control port to memory, it internally issues a software reset. the software reset clears all registers and transfers con- trol to the application now resident in ram. a hardware reset (reset pin toggled low) with the boot pin low has the same effect as a software reset. the cs4922 will boot from a micro controller us- ing the serial control port. when booting, it can communicate in an i 2 c or spi format. if the cs (chip select) pin is high when boot is initiated, the port will communicate in i 2 c format. if the cs pin is low when boot is initiated, the port will commu- nicate in spi. please refer to the timing require- ments found at the beginning of this document. nodes in an i 2 c network have unique network ad- dresses. a message in an i 2 c network consists of the address of the node receiving the message fol- lowed by the message data. when the control port is configured for i 2 c format, it normally compares the address to an address stored in an internal reg- ister. during the boot procedure, the control port is programmed to ignore the address. the scp sec- tion on i 2 c operation explains the mechanics of writing to the cs4922. the boot program in internal rom expects data transferred through the control port to adhere to a proprietary download image format. the download image always concludes with two bytes containing ff and three bytes containing a check sum. the check sum is generated by summing all the previ- ous data, address, and length bytes and truncating to 24 bits. during download, the cs4922 generates a check- sum on the download image as it is received. this check sum is compared to the value found at the tail of the download image. if they do not match, the req (request) pin is pulled low and the processor does not issue the software reset. it stays in a loop until boot is initiated again. if the download image format is corrupted to the point that the cs4922 does not know which bytes represent the check sum, then req will not drop to indicate download failure. this should never hap- pen in a stable system. during initial system testing we recommend down- loading an image that has only the check sum cor- rupted (the final 3 bytes). if req drops after the complete application code image has been trans- ferred, then the download procedure is functioning properly. if req does not drop, then there is a problem with the download procedure.
cs4922 24 6 power supply and grounding when using separate supplies, the digital power should be connected to the cs4922 via a ferrite bead, positioned closer than 1" to the device (see figure 18). the cs4922 va+ pin should be de- rived from the cleanest power source available. if only one supply is available, use the suggested ar- rangement in figure 1. the cs4922 should be positioned such that the an- alog pins (pins 29 - 39) are over the analog ground plane, while the rest of the pins lay over the digital ground plane as illustrated in figures 18 and 19. the analog and digital grounds on the cs4922 are not connected internally; this should be accom- plished externally through a point-to-point connec- tion across the ground split as shown in figure 18. a separate power plane for the chip is preferable. figure 19 illustrates the optimum ground and de- coupling layout for the cs4922 assuming a sur- face-mount socket and surface mount capacitors. surface-mount sockets are useful since the pad lo- cations are exactly the same as the actual chip; therefore, given that space for the socket is left on the board, the socket can be optional for produc- tion. figure 19 depicts mostly the top layer contain- ing signal traces and assumes the bottom or inter- layer contains a solid ground plane (analog or dig- ital), except where the digital supply needs to run to the power pins. the important points with regards to this diagram are that the ground plane is solid under the cs4922 and connects all ground pins with thick traces providing the absolute lowest im- pedance between ground pins. the decoupling ca- pacitors are placed as close as possible to the device which, in this case, is the socket boundary. the lowest value capacitor is placed closest to the chip. vias are placed near the agnd and dgnd pins, under the ic, and should be attached to the solid ground plane (analog or digital) on another layer. the negative side of the decoupling capaci- tors should also attach to the same solid ground plane. traces bringing the power to the cs4922 should be wide thereby keeping the impedance low. if using through-hole sockets, effort should be made to find a socket with the minimum height which will minimize the socket impedance. when using a through-hole socket, the vias under the chip in figure 19 are not needed since the pins serve the same function. digital ground plane note that the cs4922 is oriented with its digital pins towards the digital end of the board. digital interface analog signals & components analog ground plane 1/8" > +5v analog supply ferrite bead ground connection cs4922 figure 18. cs4922 suggested layout
cs4922 25 figure 19. cs4922 surface mount decoupling layout
cs4922 26 7 dac filter response plots figures 20 through 23 show the overall frequency response, passband ripple and transition band for the cs4922 dacs. figure 23 shows the dacs' de- viation from linear phase. fs is the selected sample frequency. since the sample frequency is program- mable, the filters will adjust to the selected sample frequency. fs is also the fsync frequency. figure 20. dac frequency response figure 21. dac phase response figure 22. dac transition band figure 23. dac passband ripple
cs4922 27 8 pin descriptions power supplies vd1, vd2, vd3, vd4 - positive digital power supply, pins 7, 17, 25, 43. the +5v supply is connected to these pins to power the various digital subcircuits on the chip. see decoupling section in this data sheet for decoupling recommendations. dgnd1, dgnd2, dgnd3, dgnd4 - digital ground, pins 6, 18, 26, 42. digital power supply ground. va+ - positive analog power supply, pin 34. the analog +5v supply for the analog-to-digital converter and the pll. analog performance is highly dependent on the quality of this supply. see decoupling section in this data sheet for decoupling recommendations. agnd1, agnd2 - analog ground, pin 33, 36. analog power supply ground. top view 18 20 22 24 26 28 1 2 4 640 42 44 12 8 10 14 16 7 9 11 13 15 17 29 31 33 35 37 39 34 30 32 36 38 cdin cs sck/scl req sda/cdout tx dgnd1 vd1 auxout auxin auxlr auxclk dbclk dbda xf4 xf3 xf2 vd2 dgnd2 90_clk xf1 sdata sclk vd4 dgnd4 reset boot aoutr aoutl aoutm agnd2 nc va+ agnd1 nc flt pio extck altclk clkin dgnd3 vd3 clkout fsync cs4922
cs4922 28 digital-to-analog converter aoutl, aoutr - analog outputs, left and right channels, pins 38, 39. these dac outputs are centered at approximately 2.2v. an external filter is required to diminish out-of-band noise. see typical connection diagram, figure 1. aoutm - mono analog output, pin 37. mono is the summation of aoutl and aoutr. mono output is 180 out-of-phase with the sum of aoutl and aoutr. mono is centered at approximately 2.2v. an external filter is required to diminish out-of-band noise. see typical connection diagram, figure 1. serial audio port fsync - frame synchronization clock input, pin 23. when sclk and sdata are used for delivering compressed data to the cs4922 (e.g. the mpeg application code), the fsync pin should be tied to the +5v supply. when sclk and sdata are used for delivering pcm data (e.g. the g.729a application code), fsync transitions delineate left and right audio data, or the start of a data frame. sclk - serial clock input, pin 22. sclk is used to clock the serial audio data on sdata into the device. the active edge of sclk is determined by the application code running on the cs4922. sdata - serial audio data input, pin 21. sdata is an audio data input pin for the cs4922. the data is clocked in on the active edge of sclk. digital audio transmitter tx - transmitter output, pin 5. biphase mark encoded data is output at logic levels from the tx pin. this output typically connects to the input of an rs-422 or optical transmitter. with additional external circuitry, the port can support either aes/ebu or s/pdif formats. clock manager clkout - clock output, pin 24. clkout can be used to synchronize peripheral devices such as a micro controller or an audio source. the clock frequency is determined by a divide by q in the clock manager. the maximum clkout frequency is the maximum dsp frequency divided by 2. altclk - clock input, pin 28. when extck is high, altclk is an input for an externally generated clock. this clock directly becomes the dsp clock and the clock frequency should be 512fs or 768fs.
cs4922 29 extck - external clock select, pin 29. setting extck high allows altclk to be used as an input for an external vco. setting extck low disables altclk. note that extck should be tied directly to either digital power or ground for proper operation. flt - pll filter, pin 31. a capacitor (typically 0.47 m f) connected to this pin filters the control voltage for the on-chip vco. trace length should be minimized to the pin. clkin - clock input, pin 27. the 27 mhz clock input to the clkin is used to synchronize the pll's. it is typical for sclk for the audio data and clkin to be derived from the same clock source to avoid asynchronous noise between the audio source and the dsp. 90_clk - optional scr/pcr 33-bit counter clock, pin 19 the 90_clk pin is an input clock signal (typically 90 khz) which is used to clock the internal 33-bit counter. the 33-bit counter's clock source is set to 90_clk when div = 0 in the cm0 register. otherwise when div = 1, the 33-bit counter will be clocked by clkin ? 300. control dbclk, dbda - debug port, pins 12, 13. it is required that a pull-up be used (typically 2.2 k w ) on pin 13. reset - pin 41. the cs4922 enters a reset state while reset is low. when in reset condition, all internal registers are set to 0, the digital audio transmitter, serial control port, and altclk pin are disabled, and the stereo dac is muted. normal operation is resumed one internal clock cycle after the rising edge of reset . boot - pin 40. boot enable pin. pin must be set high to initiate the download of a program. while boot is high, reset must be toggled high. this starts the internal boot program. xf1, xf2, xf3, xf4 - external flags, pins 20, 16, 15, 14. the xf pins are software controllable outputs via the lint register. these pins are open drain so an external pullup is required (typically 2.2 k w ) for proper operation of the pins. pio - pin 30. this pin should be grounded through a 10 k w resistor in normal operation.
cs4922 30 serial control port req - request output, pin 3. this pin is driven low when the dsp needs servicing from an external device. a write to the scpout will cause the req to go low. a pull-up resistor is required for proper operation (2.2k w is typical). cs - chip select input, pin 44. in spi format, all communication between the host and the cs4922 is initiated when the host drives the cs pin low. this pin also serves as the communication format select during a reset or power up. when cs is high during a reset or power up the scp will be configured in i 2 c ? mode. when low, it is configured in spi mode. the mode is selectable in software by setting the m0 bit in the scpcn. sck/scl - serial clock input, pin 2. sck/scl clocks data into or out of the serial control port. this is always driven by an external device because the cs4922 always operates in slave mode. sda/cdout - serial data i/o / control data output, pin 4. in spi mode, cdout is a data output for the serial control data. in i 2 c interface mode, sda is a bi-directional data i/o. it is required that a pull-up be used (2.2 k w is typical in i 2 c mode). cdin - control data input, pin 1. in spi mode, cdin is the data input for the serial control port. it has no function in i 2 c mode. the pin should be connected to either digital power or ground when the cs4922 is used in i 2 c systems. auxiliary digital audio port auxlr - auxiliary sample clock, pin 10. this output signal determines which channel is currently being input on the auxin pin or output on the auxout pin. it is also the sample clock, fs. auxin - auxiliary data input, pin 9. twos complement msb first serial data is input on this pin. the data is clocked by auxclk and the channnel is determined by auxlr. auxout - auxiliary data output, pin 8. twos complement msb first serial data is output on this pin. the data is clocked by auxclk and the channel is determined by auxlr. auxclk - auxiliary serial clock output, pin 11. this is the auxiliary audio port serial clock output. this output is used to clock data in on the auxin pin and shift data out on the auxout pin. its frequency is selectable in software.
cs4922 31 9 parameter definitions resolution the number of bits in the input words to the dacs. differential nonlinearity the worst case deviation from the ideal codewidth; expressed in lsbs. total harmonic distortion (thd) thd is the ratio of the test signal amplitude to the rms sum of all the in-band harmonics of the test signal. instantaneous dynamic range the signal-to-(noise + distortion) ratio (s/(n+d)) with a 1 khz, -60 db from full scale dac input signal, with 60 db added to compensate for the small signal. use of a small signal reduces the harmonic distortion components of the noise to insignificant levels. units are in db. interchannel isolation the amount of 1khz signal present on the output of the grounded input channel with 1 khz, 0db signal present on the other channel. units are in db. interchannel gain mismatch the difference in output voltages for each channel with a full scale digital input. units are in db. frequency response worst case variation in output signal level versus frequency over 10 hz to 20 khz. units in db. out of band energy the ratio of the rms sum of the energy from 0.46 fs to 2.1 fs compared to the rms full-scale signal value. tested with 48 khz fs giving a out-of-band energy range of 22 khz to 100 khz.
cs4922 32 10 package dimensions inches millimeters dim min max min max a 0.165 0.180 4.043 4.572 a1 0.090 0.120 2.205 3.048 b 0.013 0.021 0.319 0.533 d 0.685 0.695 16.783 17.653 d1 0.650 0.656 15.925 16.662 d2 0.590 0.630 14.455 16.002 e 0.685 0.695 16.783 17.653 e1 0.650 0.656 15.925 16.662 e2 0.590 0.630 14.455 16.002 e 0.040 0.060 0.980 1.524 jedec # : ms-018 44l plcc package drawing d1 d e1 e d2/e2 b e a1 a
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